1. Field of the Invention
The invention lies in the semiconductor technology field. More specifically, the present invention relates to a method of creating cavities that are structured in submicrometer dimensions in a cavity layer of a semiconductor device by polymerization, and to a configuration which is produced by the method, with cavities that are structured in submicrometer (submicron) dimensions in a semiconductor device.
Inside a semiconductor device, conductive tracks are capacitively coupled to one another both within an interconnect layer (intralevel) and between different interconnect layers (interlevel). Such capacitive coupling between conductive tracks leads to crosstalk and to extended signal transit times.
In order to minimize these disruptive effects, the conductive tracks are decoupled from one another as much as possible by minimizing the capacitance between them. Given a defined spacing between two conductive tracks, this requires an optimally low permittivity of the material between the conductive tracks. Gaseous substances such as air have an almost optimal permittivity of near 1 at normal pressure, whereas the permittivity of solid bodies is usually substantially higher.
For this reason, in semiconductor devices it is generally desirable to decouple two tracks from one another by air-filled cavities. The prior art methods for creating such air gaps will be described below. All these methods presume a working layer which has already been structured by ridges and trenches.
Conductive tracks can functionally emerge from the ridges of the working layer. The trenches of the working layer are cavities which have not yet been covered. Accordingly, an interconnect layer is one possible embodiment of a cavity layer that emerges from a working layer, but not the only one.
According to a first method, the trenches are filled with porous materials such as xerogels or aerogels and then covered with a dielectric coverlayer. The air that is trapped in the pores lowers the overall permittivity of the material between the tracks. Such porous materials are in the evaluation phase at present. The disadvantages of these methods are the water absorption owing to the capillary effect of the open-pored structures, and the relatively long processing times. Furthermore, filling the cavities with material of the xerogels and aerogels raises the permittivity of the cavity relative to a pure air fill. The utilization of aerogels as dielectric materials with low permittivity is described in xe2x80x9cThe Effect of Sol Viscosity on the Sol-Gel Derived Low-Density SiO.sub.2 Xerogel Film For Intermetal Dielectric Applicationxe2x80x9d (Thin Solid Films, vol. 332, pages 449-54, 1998).
A second method is to cover trenches by conventional SiO2-CVD-processes (Chemical Vapor Deposition) with a high deposition rate.
A first variant of such a method is described in xe2x80x9cAir-Gap Formation During IMD Deposition to Lower Interconnect Capacitancexe2x80x9d (B. P. Shieh, IEEE Electron Device Letters, vol. 19, no. 1, pp. 16-18, January 1998). But gaps which are generated in this fashion extend into the SiO2 coverlayer (cap formation). In subsequent CMP processes, the underlying cavities can be opened, and neighboring conductive tracks can be shorted by a subsequent metallization in these open cavities. If the SiO2 layer is deposited with sufficient thickness to prevent a subsequent opening of the cavities, then the problem of contacting underlying tracks by way of sufficiently deep vias arises.
In a variant of this method which is described in xe2x80x9cA Novel Air Gap Integration Scheme for Multi-Level Interconnects Using Self-Aligned Via Plugsxe2x80x9d (T. Ueda, Symp. on VLSI Technology, pp. 46, 47, June 1998), the covering of the trenches is a two-stage process. In a first stage, SiO2 is deposited on the horizontal surfaces of the ridges with a PECVD (Plasma Enhanced Chemical Vapor Deposition) method. Narrow trenches are thus covered by SiO2 that grows on both sides of the trenches on the surfaces of the ridges. In an HDP-CVD process (High Density Plasma CVD), wider trenches are then filled with SiO2 and narrow trenches are sealed with SiO2.
According to a third method, as described in xe2x80x9cUse of Air-Gap Structures to Lower Intralevel Capacitancexe2x80x9d (J. G. Fleming, E. Roherty-Osmum, Proc. DUMIC, pp. 139-45, 1997), spin-on materials are employed for covering the cavities between the tracks. The disadvantage of that method is the backflow of the materials into the cavities.
A fourth method is described in PCT publication WO 97/39484 A1 (Rosenmayer, Noddin). A film is laid on the interconnect layer that is structured by trenches and ridges. Such a film has a thickness of at least several micrometers, so that it can be safely processed. This gives rise to large spacings between the interconnect planes as described above, with the described disadvantages in connection with through-contacting by means of vias.
A fifth method, described in U.S. Pat. No. 6,165,890 (Kohl), is the retropoly-merization of polynorbornene, which temporarily fills the cavities between the interconnects. In this method, unavoidable residues of the retropolymerization can lead to clusters that pose a short-circuiting risk. Furthermore, the selection of the dielectric material between interconnect layers is limited, because the material must be permeable to the volatile substances that emerge in the retropolymerization.
Similar disadvantages arise in a sixth method, the thermal decomposition of a temporary filling of the cavities between the conductive tracks. An example of a thermal decomposition of a temporary filling with a photoresist is described in U.S. Pat. No. 5,668,398 (Havemann). The oxidation of a temporary carbon layer is described in xe2x80x9cNURA: A Feasible Gas Dielectric Interconnect Processxe2x80x9d (M. B. Anand, M. Yamada, H. Shibata, Symp. on VLSI Technology, pp. 82, 83, June 1996). In both cases, the substances which emerge in the decomposition must be expelled through the coverlayer, which limits the material selection. The undecomposable residues in the cavities raise the permittivity, thereby reducing the resistance to shorting. According to another known example of the decomposition of a temporary filling, which is described in the PCT publication WO 00/51177 (Werner, Pellerin), the coverlayer is perforated prior to the decomposition of the filling in order to accelerate and thus improve the expulsion of the decomposition residues.
According to a seventh method, described in U.S. Pat. No. 5,599,745 (Reinberg), a dielectric layer is deposited on the ridges that are formed by the conductive tracks, this is melted enough that this layer arches over the track, and arches of the coverlayer of closely adjacent tracks ultimately touch, bridging the trenches between them.
An eighth method for generating air gaps is described in U.S. Pat. No. 6,251,798 B1 (Soo et al.). There, in a first step a plasma-polymerized methyl silane is deposited on a structure consisting of metal ridges such that it also fills the intermediate spaces between the metal ridges. The layer of plasma-polymerized methyl silane over the metal ridges is cured in sections by exposure. The plasma-polymerized methyl silane over the intermediate spaces between the metal ridges is partly covered during exposure, so that channels consisting of uncured plasma-polymerized methyl silane are formed from the surface to the spaces between the metallized ridges, which spaces are filled with uncured plasma-polymerized methyl silane. In a subsequent etching step, the uncured plasma-polymerized methyl silane is selectively etched against the cured plasma-polymerized methyl silane. It is removed also from the spaces between metallized ridges by way of the channels.
The disadvantage of this method is, first, that the curing must be adapted to the thickness of the deposited plasma-polymerized methyl silane layer. Furthermore, the plasma-polymerized methyl silane layer must be provided with a thickness of at least some 500 nanometers in order to achieve sufficient mechanical stability of the layer.
Similarly, according to a ninth method, described in U.S. Pat. No. 6,268,277 (Bang), spaces between metallized ridges are etched through channels that are provided in a coverlayer. But such techniques already require coverlayers which are sufficiently stable even in a perforated condition. Besides, the photolithographic processes which are needed for constructing the etch channels in the coverlayer must manage smaller structural dimensions than are needed for constructing the ridges in the cavity layer. Because the coverlayer must furthermore comprise a layer thickness of several 100 nanometers, the etch channels are also relatively long given a small diameter, and thus etching residues remain in the formed cavities.
In a tenth method for forming air gaps, a polyimide is deposited surface-wide on a layer which has been structured by trenches and ridges. In a subsequent processing step, additional dielectric material is deposited on the polyimide. The dielectric material is deposited in a first step at a temperature at which significant outgassing from the polyimide occurs. With the outgassing, cavities form between the polyimide layer and the overlying dielectric material. But the spaces between metallized ridges cannot be realized as even close to completely empty cavities with this rather simple method which requires no further structuring measures. That method is described in U.S. Pat. No. 5,783,481 (Brennan).
The article xe2x80x9cAir Gaps Lower K Of Interconnect Dielectricsxe2x80x9d (Ben Shieh, Krishna Saraswat, Mike Deal, Jim McVittie, Solid State Technology, February 1999) contains a summary of known methods for generating air gaps in a semiconductor substrate, together with an appraisal of the results they achieve.
To summarize, the disadvantages of the described methods are rooted in:
residues in the cavities, which raise the permittivity and/or diminish the resistance to shorting;
the required thickness of the layer covering the trenches and the associated difficulty in realizing vias;
the process integration.
It is accordingly an object of the invention to provide a method with which structured cavities with submicrometer dimensions can be created in a cavity layer of a semiconductor device, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which, while providing the possibility of utilizing process techniques, materials and means that are common in semiconductor processing technology, advantageously leads to cavities that are free of residues, and a layer that covers the cavity layer with a thickness that does not exceed one micrometer.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of forming structured cavities with submicrometer (submicron) dimensions in a cavity layer of a semiconductor device, which comprises the following steps:
depositing an initially compact working layer on a base layer, the working layer being formed, at least in sections thereof, of a working material;
depositing a processing layer on the compact working layer to form a double layer from the working layer and the processing layer, the processing layer containing polymerizable processing material;
structuring the double layer to form ridges of submicrometer dimensions of the working material covered by the processing material, and to form trenches between the ridges;
polymerizing the processing material and growing additional material on mutually adjacent ridges, to cover respective trenches between the ridges, and forming cavities; and
expelling processing residue from the cavities.
In other words, the objects of the invention are achieved with the following numbered method steps:
(1) deposit an initially compact working layer, which consists of a working material at least in sections, on a base layer;
(2) deposit a processing layer on the compact working layer, whereby a double layer emerges from the working layer and the processing layer, and whereby the processing layer comprises at least one active processing sublayer consisting of a polymerizable processing material
(3) structure the double layer, creating ridges with submicrometer dimensions from the working material, which are covered at least by the processing material, and between the ridges, trenches;
(4) control a polymerization of the processing material, whereby additional material grows on the processing material on neighboring ridges, such that trenches between the ridges are covered and cavities are formed; and
(5) expel processing residues from the cavities.
In the inventive method, an initially compact working layer is deposited on a base layer, and a processing layer is deposited on the working layer, so that a double layer composed of the working layer and the processing layer emerges.
The processing layer can be composed of several processing sublayers. But in any case it comprises at least one active processing sublayer consisting of a polymerizable processing material. The active processing sublayer preferably lies directly on the working layer.
The double layer consisting of the processing and working layers is then structured. There emerge ridges consisting of a working material, which are covered at least by the processing material, and between the ridges, trenches. The ridges and trenches have submicrometer dimensions.
Residual portions of the processing material are suitably prepared so that they excite a subsequent polymerization, preferably in the lateral direction parallel to the base layer, wherein material grows on the processing material.
A first method of achieving this is to cover the active processing sublayer with a passive processing sublayer in the vertical direction parallel to the base layer.
The active processing sublayer is thus shielded at the surfaces parallel to the base layer, while side surfaces on the flanks of the ridges remain clear. This way, additional material can be selectively grown.
A second method is to reinforce the surface of the active processing sublayer opposite the working layer, so that the growth of material at this surface during a polymerization process is inhibited. In this case, the active processing sublayer can also be the only processing sublayer of the processing layer.
The polymerization of the processing material occurs in a controlled fashion. The processing material expands primarily parallel to the base layer. The layers of the processing material on neighboring ridges thus grow toward one another and ultimately cover the trenches.
The polymerization is interrupted as soon as the overhanging expanding processing material covers trenches whose width is less than a maximum cover-width.
Cavities emerge with the covering of the trenches and the removal of processing residues from the trenches.
The base layer is advantageously constructed as an etch stop layer which is resistant to the etching of the working layer. The material of the working layer can be completely removed in etched portions without having to make further demands on a process control, for instance with respect to controlling the etching period. This simplifies the structuring of the working layer.
If the material of the ridges of the working layer is a conductive material such as copper, then a cavity layer which is developed from the working layer is realized as an interconnect layer.
On the other hand, if the cavity layer is intended for a capacitive decoupling of two interconnect layers, then a dielectric material with low permittivity is selected as the material of the ridges.
The trenches in the working layer reach the base layer, in order to achieve an optimally high overall permittivity between neighboring ridges that are realized as conductive tracks.
The polymerization is advantageously performed as graft polymerization.
The structuring of the double layer consisting of the compact working layer and the processing layer can be performed in various ways.
A first method starts with a compact, homogenously developed working layer consisting of the conductive material, and on this, a processing layer.
A photoresist is deposited on the processing layer and structured. Next, the structure of the photoresist is imaged onto the processing layer, and then the structure of the processing layer is imaged onto the working layer.
The photoresist is advantageously used up in the structuring of the working layer. But it can also be removed in a separate step or can remain on the processing layer.
The material of the processing layer is advantageously a fluorinated hydrocarbon (a-C:H(F)).
The processing layer is usually structured with an etching method. Therefore, after the photoresist is structured, the etch resistance of its residual-portions is reinforced.
The reinforcing is advantageously accomplished by silylation.
A group containing silicon is thereby incorporated into the photoresist. The photoresist includes corresponding reactive groups.
A second method for structuring the double layer of the working and processing layers starts with a compact working layer which is prestructured from the working material and an auxiliary material by the customary technique. The prestructured working layer already includes first portions consisting of the working material and second portions which consist of the auxiliary material. The ridges will be formed from the first portions, and the trenches will be formed from the second portions. At the surface of the working layer opposite the base layer, the working layer comprises a working surface, which is formed in sections from the surfaces of the first portions (which consist of the auxiliary material) and the surfaces of the second portions (which consist of the working material).
In a first step of the second method for structuring the double layer of working and processing layers, the processing layer is structured in such a way that it remains on portions of the working surface formed from the working material and is removed from the portions of the working surface formed from the auxiliary material.
Next, in a second step, the auxiliary material is removed.
In a first variant of the structuring of the processing layer on a prestructured working layer in the course of structuring a double layer of the processing and working layers, the processing material is a positive photoresist which is suitable for polymerization.
The structuring of the processing layer then occurs directly by lithography. Surfaces of residual portions of the processing layer opposite the working layer can be reinforced so that a subsequent polymerization advantageously occurs laterallyxe2x80x94on the surfaces oriented vertical to the base layer, which were cleared by the structuringxe2x80x94and thus parallel to the base layer.
In a second variant of the structuring of the processing layer on a prestructured working layer in the course of the structuring of a double layer of the processing and working layers, the processing layer is provided in the form of an active processing sublayer consisting of a polymerizable processing material and a passive processing sublayer. The active processing sublayer lies on the working layer, and the passive processing sublayer lies on the active processing sublayer. The passive processing-sublayer is inert to polymerization. It consists of an amorphous hydrocarbon layer (a-C:H), for instance.
The structuring is achieved by depositing, exposing and developing an auxiliary photoresist according to the structure of the working layer. Residual portions of the auxiliary photoresist remain over the first portions, which will be developed into ridges, of the prestructured working layer consisting of the working material and are separated from said first portions by the processing layer.
The structure of the auxiliary photoresist is then transferred into the processing layer.
The removal of the auxiliary photoresist is advantageously accomplished during the removal of the auxiliary material from the working layer. A plasma which erodes both the auxiliary photoresist and the auxiliary material is used for this.
But the auxiliary photoresist can also be removed in a separate step before or after the auxiliary material is removed. Its residual portions can also remain on the processing layer if the material of the auxiliary photoresist is a material of low permittivity and can be processed the same way as a subsequently applied coverlayer in a later etching process, for instance for generating vias.
The active processing sublayer in this variant advantageously comprises a sensitizer. The sensitizer is advantageously a benzophenone, benzopyrone, or thioxanthone derivative.
The passive processing sublayer is an amorphous hydrocarbon which protects the active processing sublayer during the developing of the overlying auxiliary photoresist and/or which inhibits a subsequent polymerization of the active processing sublayer in a vertical direction perpendicular to the base layer.
The etch resistance of the auxiliary photoresist can be reinforced after the developing process.
With the above described methods and variants, a structure with submicrometer dimensions consisting of ridges and trenches is generated in the working layer. The ridges bear caps consisting of the material or materials of the processing layer, which can take one of the following forms, depending on the method applied for structuring the double layer of working and processing layers:
a single-layer cap consisting of a polymerizable material, whereby the surface of the cap opposite the working layer is prepared such that it polymerizes little if at all;
double-layer cap, whereby an additional non-polymerizable sublayer lies on a bottom polymerizable sublayer and impedes growth vertical to the base layer.
Proceeding from such a structure of at least double-layer ridges on the base layer, in the next stage of the inventive method a polymerization of the processing material is controlled.
In a first substep, the polymerization is triggered, and in a second substep it is perpetuated.
The sequence of initiation and perpetuation constitutes a process cycle that is repeated until the processing material on the ridges, which expands in an overhanging fashion owing to the incorporation of monomers, covers trenches between neighboring ridges whose width at their top edge is less than a maximum cover width.
In a first preferred technique, the polymerization is triggered by exposure of the processing material.
In a second preferred technique, the polymerization is initiated by radical starter compounds.
According to a first embodiment of the inventive method, the monomers are supplied in the gas phase.
According to a second embodiment, the monomers are applied to the processing material in a solution.
The polymerization is ended by heating to a first temperature.
In the polymerization, monomers and if in solution, the solventxe2x80x94are trapped in cavities that emerged with the covering of the trenches. These processing residues can be expelled from the cavities by heating to a second temperature.
The first and second temperatures are advantageously the same, so that both processes occur in one step.
A coverlayer consisting of a dielectric material with low permittivity can be deposited on the polymerized processing layer (which is typically only 20-200 nm thick) in the next processing stage. The dielectric material is advantageously an organic dielectric material. This can be polybenzoxazole, polyaryl ether, hydrogen silsesquioxane, a fluorinated organic silica CVD film or a fluorinated or non-fluorinated hydrocarbon. Vias can then be etched into the double layer of the polymerized processing layer and the coverlayer (which is composed of an organic dielectric material) by the same means in one processing step.
Silicon dioxide is also a suitable material for the coverlayer.
The capacitive coupling of two conductive tracks which are developed from ridges is dependent on the permittivity of the material separating the tracks and the spacing of the tracks from one another. Given a greater spacing of the tracks, a higher permittivity of the material between the tracks can be allowed in order to achieve the same capacitive coupling.
Given a large spacing of neighboring ridges, to the extent that trenches are not covered by expanding processing material and are filled with a material of low permittivity, there is no disadvantage to such open structures in practice.
A semiconductor device which has near ideal cavities in a cavity layer is generated with the inventive method. The cavities have close to the lowest possible permittivity. Conductive tracks that are developed from ridges which adjoin such cavities are decoupled from one another to the greatest possible extent.
With the above and other objects in view there is also provided, in accordance with the invention, a configuration in a semiconductor device, comprising:
a base layer;
a cavity layer on said base layer, said cavity layer being structured in submicrometer dimensions with ridges of a working material and cavities therebetween; and
a processing layer formed of a cured polymer supported on said ridges and covering said cavities, said processing layer having a thickness of less than 100 nanometers.
In other words, the configuration in the semiconductor device comprises a base layer; a cavity layer on the base layer, with a structure with submicrometer dimensions, which consists of ridges of a working material and cavities; and a polymerized processing layer on the ridges, which covers the cavities.
In accordance with an added feature of the invention, the processing layer advantageously has a thickness of less than 100 nanometers.
The base layer advantageously consists of an etch stop layer such as silicon nitride.
In an advantageous variant of the configuration according to the invention, the ridges consist of a conductive material, particularly of copper.
The configuration can be expanded by a coverlayer which lies on the polymerized processing layer.
The coverlayer advantageously consists of an organic dielectric material, so that the coverlayer and the processing layer can be processed by the same means, for instance during the subsequent creation of vias.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method and a device with cavities having submicrometer dimensions in a semiconductor device which are generated by polymerization, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.